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Company profile

Ensilica PLC

EnSilica - Turnkey ASIC Design and Supply

Your trusted IC partner for custom asic design and supply and full-flow IC design services with expertise in analog, mixed signal and digital domains.

CRN
04220106
Founded
2001
Age
25

Overview

Legal name
ENSILICA PLC
Region
South East England
Registered address
100 PARK DRIVE
MILTON PARK
ABINGDON
OXFORDSHIRE
ENGLAND
OX14 4RY
Insolvency history
No

Company events

Reference milestones and recent Companies House filing stream events.

11 events
04 Jun
2027

Confirmation statement due

Confirmation Due

Next confirmation statement due date

30 Nov
2026

Accounts due

Accounts Due

Next accounts due date

21 May
2026

Confirmation statement filed

Confirmation

Last confirmation statement made up date

31 May
2025

Accounts filed

Accounts

Last accounts made up date

12 Nov
2024

Mortgage Satisfy Charge Full

Mortgage

MR04 | Transaction MzQ0Mjc3OTYyMGFkaXF6a2N4

Published 12 Nov 2024 09:28

05 Nov
2024

Mortgage Create With Deed With Charge Number Charge Creation Date

Mortgage

MR01 | Transaction MzQ0MjA1MjE3OWFkaXF6a2N4

Published 08 Nov 2024 12:51

04 Nov
2024

Mortgage Satisfy Charge Full

Mortgage

MR04 | Transaction MzQ0MTkyMTEzOGFkaXF6a2N4

Published 04 Nov 2024 04:56

21 Oct
2024

Appoint Person Secretary Company With Name Date

Officers

AP03 | Transaction MzQ0MDI2NzM4M2FkaXF6a2N4

Published 21 Oct 2024 08:54

21 Oct
2024

Termination Secretary Company With Name Termination Date

Officers

TM02 | Transaction MzQ0MDI2Njk3N2FkaXF6a2N4

Published 21 Oct 2024 08:52

08 Aug
2024

Mortgage Satisfy Charge Full

Mortgage

MR04 | Transaction MzQzMTYyNzIzNmFkaXF6a2N4

Published 08 Aug 2024 14:04

21 May
2001

Incorporated

Inception

Company registered at Companies House

Public funding

4 awards
First funded
2013
Funded years
2013, 2014, 2015
Age at first award
11 years

Projects

2015 Collaborative R&D Lead participant

Expanding and Improving Adiabatic Logic in the eSi-RISC CPU

1 Jun 2015 to 30 Nov 2017

Awarded
£203,928
Total cost £339,880

Static CMOS circuit design is ubiquitous in digital ASICs and SoCs, and is preferred over other logic families due to its low power consumption. However, power consumption is still a problem for many battery powered devices using static logic and the problem of dark silicon is predicted as CMOS scaling continues. An alternative, yet commercially unexploit...

2014 EU-Funded Lead participant

ARTEMIS EMC2(AIPP)

1 Apr 2014 to 30 Jun 2017

Awarded
£78,104
Total cost £187,975

Awaiting Public Project Summary

2013 Feasibility Studies Lead participant

Applying Adiabatic Logic to the eSi-RISC CPU

1 Apr 2013 to 31 Jan 2015

Awarded
£62,842
Total cost £109,101

Static CMOS circuit design is ubiquitous in digital ASICs and SoCs, and is preferred over other logic families due to its low power consumption. However, power consumption is still a problem for many battery powered devices using static logic and the problem of dark silicon is predicted as CMOS scaling continues. An alternative, yet commercially unexploit...

2013 Vouchers Lead participant

Luminaire control system

1 Apr 2013 to 31 Oct 2013

Awarded
£5,000
Total cost £5,000

We are looking at producing a reference design for LED luminaire lighting control. As part of this activity we are generating our own hardware including a Xilinx Zynq SoC using fast 533MHz DDR3. This will form the controller module for the end application that will control a 5 colour LED light fitting, Red + Amber + Green + Cyan + Blue. This allows us to ...

Product types

Collaborative R&D EU-Funded Feasibility Studies Vouchers