Public Funding for Arm Limited

Awaiting Public Project Summary

Building awareness of the semiconductor industry and filling key gaps in the workforce is a critical part of the UK's knowledge economy strategy. To move the needle, it is necessary to intervene at every stage of the talent pipeline -- from schools, through universities, all the way to continuous professional development for experienced engineers/career switchers. Both scale and depth matter. King's College London (KCL) and Arm are world-leading UK academic and semiconductor industry players respectively. By working in partnership together with the UK Electronic Skills Foundation (UKESF), KCL will create a set of coherent learning pathways, by leveraging existing resources and producing new ones, which will: * Draw young people in from diverse backgrounds who haven't previously considered a semiconductor-related career in the UK * Provide education and training to undergraduates and early career professionals studying/working in adjacent subject areas, to encourage career development/switching * Add post-graduate semiconductor specific skills and knowledge to those already committed to an engineering track to ensure their long-term involvement in the industry The programme will take a broad view, covering fundamental science knowledge, manufacturing and applications, informed by the visions, needs and recruiting requirements of industry partners (co-ordinated by UKESF). The Holistic Open-Stop Semiconductor Curriculum (HOSC) will include material, IC design, simulation, package, testing, electronic circuit/system, application, management and industry-academia joint individual/group projects. Multiple entry points will be available, encompassing both undergraduates and postgraduates, industrial graduate engineers via induction courses, and re-skilling for more established engineers. The curriculum will be modular in nature including educational kits, assessments and dedicated mentoring and support will be available for Black, Women, Asian and minority ethnic learners. Industry partners will be able to access training to meet their own skills and productivity gaps. Semiconductor industry awareness-raising will also be an explicit aim. KCL will facilitate a series of engagement workshops in which industry partners will outline their view of contemporary skills requirements, enabling networking and the exchange of ideas as well as a platform for continuous professional development and recruitment. By addressing the full gamut of needs with broad and deep interventions and exploiting the network effects of bringing the best of academia and industry together, the programme will make a meaningful contribution to the national supply of talent, accelerate time to market and draw more people. There will be a special focus on schools' outreach, equality diversity and inclusion in practice, communication and delivery so that everyone can take part.

Piccolo will offer foundational technology breakthroughs for the long-term evolution of mobile networks, including 5G and beyond, enabling those networks and their operators as well as new market entrants to support newly emerging applications and services -- and thus also foster broad innovation. As key technology, Piccolo will introduce an unprecedented blending of networking, computing and data storage capabilities in a uniform in-network computing architecture. This platform will allow flexible, easy, and impromptu instantiation of applications across network nodes, close to the user, by combining lambda functions using lightweight and secure virtualisation techniques. The instant and ephemeral nature of the Piccolo approach will nicely complement (and be able to interact with) the presently standardised mobile edge computing and its service creation model. Piccolo will drive its development from two demanding use cases related to privacy-preserving data processing: 1) in the automotive domain for blending in-car and edge computing for data processing and control loops; and 2) in the area of Internet of Things for IoT vision processing and associated AI. Piccolo will develop new solutions for in-network computing that remove known and emerging deficiencies of edge/fog computing. Our vision is that every node includes processing, storage and networking capabilities in an integral architecture. The technical focus is twofold: (1) Compute platforms for network and 3rd party functions addressing fast, lightweight, secure virtualisation and data plane isolation ; (2) Distributed systems to ensure the network is scalable, resilient and secure, and supporting the joint optimisation of compute, network, and storage resources. Our objective is to create an Internet principle of "transparent in-network computing" that complements today's "transparent networking" and so enables a fresh dimension for permissionless innovation and growth. Piccolo will deliver new technical concepts, architecture and mechanisms, underpinned by an understanding of the use cases for in-network computing. Those will be realised in (open) software systems, extensively evaluated in several use cases, and disseminated via software, (pre-)standardisation efforts, and, ultimately, enhanced products of the partners.

Without an operating system, computers would be much less useful. Before the invention of operating systems, computers could only run one calculation at a time. All tasks had to be scheduled by hand. Operating systems automate the scheduling of tasks and make sure that resources such as memory and disk space are allocated properly. Because operating systems simplify computers, everyone can handle them and benefit from them. Quantum computers are a new type of powerful computer. Big and high-quality quantum computers can outperform conventional computers at specific tasks, such as predicting the properties of a drug. Currently, it is difficult for users to interact with quantum computers because there is no good operating system. The systems that exist don't schedule tasks optimally and cannot perform calculations quickly. Building this operating system is difficult -- many have tried and no solutions have worked. We have invented an operating system to overcome this technical challenge: NISQ.OS. While competitors present quantum computers as a "black box", NISQ.OS exposes all its different elements. Many of them look far more familiar than you might think. Quantum computers consist of a quantum processing unit, which contains the qubits, a couple of layers of special-purpose chips that control the qubits, and a conventional computer for overall control. By providing access to all these layers of the "quantum computing stack", we give the user the power to schedule tasks in an optimal way. This will improve the performance of quantum computers by a 1,000-fold compared to other leading approaches. Once we integrate hardware and software tightly, we expect that the performance will improve by 1,000,000-fold. We have assembled a group of experts from across the UK to build the operating system. This includes the UK's leading quantum hardware companies, Hitachi, Oxford Quantum Circuits, SeeQC, Duality Quantum Photonics, Oxford Ionics, and Universal Quantum; Riverlane, a quantum software company; Arm, a UK-based chip manufacturer; and the National Physical Laboratory. The National Physical Laboratory plays an important role because their expertise lies in developing technical standards for breakthrough technology. To build our operating system, we need to define a new standard interface between software and hardware that everyone can use. Our project will attract many important customers, such as pharmaceutical or chemical companies, as well as the financial industry. Because our operating system is so much better, they will want to run their applications on UK-based quantum computers.

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

Scope: The development and evaluation of central technologies, providing a radically new hardware architecture for securing the execution of software, along with the tools to develop application software and systems based on it (hardware architecture and implementation, System on Chip integration, platform innovation, system verification and mathematical proof, runtime languages and libraries). Deliverables: Technology Platform Prototype along with the necessary enabling system software which will be shared openly with academia and industry. Output: Creation of the compelling industry-scale, new, fundamental, centrally secured technology platform prototype (hardware and software).

The main motivation for this project is to open new market opportunities in radio frequency identification (RFID), the Internet of Things (IoT) and other flexible electronics applications, through the development of low-cost flexible p-type transistors (PMOS) to complement existing amorphous oxide n-type (NMOS) capability. NMOS based logic is sufficient for initial RFID applications in flexible electronics but complementary logic (CMOS), formed from combining n-type and p-type devices in single logic elements, is both lower power and faster than either NMOS or PMOS alone. As the overall power budget is often constrained (e.g. in mobile phones) then improved power consumption provides opportunities in increasing circuit complexity or areas requiring very low power. To date, commercially viable inorganic PMOS materials have not been identified. The project focuses on a targeted evaluation of the parameter space of novel P-type metal oxide based semiconductors, using high throughput thin film techniques proven for rapid identification and screening of the processing and composition space of functional thin film materials . Through this there will be demonstration of thin film transistor performance capable of implementation in a cost-effective flexible CMOS technology. This will be supported by SPICE modelling and circuit simulation to demonstrate expected circuit performance.

Future flexible electronic devices will be highly integrated, diversified, and interact with the ambient environment by performing intelligent activities such as fingerprint, vein and odour recognition. These devices will require a flexible high-performance, energy-efficient processor, and it is becoming clear that flexible microcontrollers, which are still in research labs, will not meet the computational demands of future smart applications. Hence, there is an immediate need for a flexible high-performance energy-efficient processing engine to deliver these devices. We propose “plastic Neural Networks (NNs)” as the digital processing engine to accelerate the development of flexible integrated smart systems. The NNs are customised for a specific application, capable of operating in extremely parallel fashion to achieve high performance, and consume low power. The project is the first proposal to pioneer digital hardware NNs as de-facto processing engine of the printed electronics world. It will demonstrate this disruptive concept with a prototype consisting of flexible e-nose sensor array coupled with a plastic NN that can be worn under the armpit to recognise the malodour composition.

Flexible electronics is a key enabler for embedded systems to deliver the Internet-of-Things, where sensors and actuators embedded in physical objects are connected to the Internet. Objects which can both sense their environment and communicate, provide important new data which can be used to respond, e.g. to protect temperature-sensitive goods, report a fault, track goods through supply-chain. One of the key enabling factors for the IoT is the convergence of emerging electronics (flexible, low-cost and simple) with conventional electronics (complex, rigid and expensive). In order to maximise the opportunity for flexible ICs, it is necessary to develop CMOS circuits, which use both n-type and p-type semiconductors. This project will investigate the feasibility of integrating a p-type oxide material into an existing NMOS process, in order to produce CMOS circuits and the viability of manufacturing scale-up.roject Summary

The UK has world leading technology for monitoring high performance computing (HPC) systems and for compiling programs for energy efficiency. This project brings these technologies together to provide an end-to-end system to significantly reduce the energy used by such systems, using the STFC's HPC facilities to demonstrate its effectiveness. Advancing such technology carries risks, but made possible through Innovate UK support. As well as HPC, the technology is applicable to the much larger data centre market, the annual electricity bill for which is $7.6Bn in the US alone. This project has the potential to reduce that by 20%. This will yield commercial benefits to the industrial participants, all small, export based UK companies addressing this global market as well as to the wider UK economy. It will also have major environmental benefits, by reducing CO2 emissions.

Awaiting Public Project Summary