Public Funding for Surecore Limited

With the advent of AI an ever-increasing amount of energy is required for computing. Moore's law is slowing as circuit dimensions approach physical limits. Quantum computers can create a computational space much larger than their classical counterparts. They will shape computing, science and commercial standards by solving numerical problems that are currently out of reach in fields including chemistry, material science, logistics, machine learning and cryptography. The race is on to build the world's first practical quantum computers, which requires scaling from arrays of a few dozen qubits to thousands and then on to millions of qubits. To achieve this we need to create integrated systems of qubit arrays and control electronics. In most implementations, the qubits require cryogenic cooling, typically to a fraction of a degree above absolute zero. Yet conventional silicon chips are designed to operate at room temperature, and if these chips are cooled to cryogenic temperatures, the operating characteristics of the transistors change markedly, and they no longer work as intended. We are working in a consortium of UK Quantum Technology experts to develop new cryogenic transistor simulation models, and based on these, a range of cryogenic CMOS memories. These will allow Quantum Computer developers to design custom cryogenic control chips and thus migrate their room temperature control electronics into the cryostat with the qubits themselves thereby accelerating their scaling potential. SureCore is an expert in the field of low power memory design with demonstrated power savings of up to 50%. In chip design memory is an essential building block storing both program code as well as the data captured from external sources to be processed. Careful management of power dissipation within the cryostat is critical, hence the importance of utilising low power solutions. To validate these memories, we have developed a test chip integrating various sizes/configurations of the memory types with sureCore's proven verification architecture. This utilises Built-In-Self-Test and a custom designed evaluation system to test memories across a range of operating voltages and speeds. Proving they work at cryogenic temperatures, as well as demonstrating that their power and timing performance meet expectations, is critical to ensure market acceptance. This A4I project will address a range of cryogenic test challenges. These include the housing of the test chip in a cryogenic chamber at 4K whilst remotely connected to the evaluation system, external to the chamber, which is responsible for driving various tests and monitoring responses.

Modern life is unthinkable without computers. An ever-increasing amount of energy is required for computing, impacting the global drive to a low-carbon economy, and Moore's law is slowing as the circuit dimensions approach physical limits. Quantum computers can create a computational space much larger than their classical counterparts. They will shape computing, science and commercial standards by solving numerical problems that are currently out of reach in fields including chemistry, material science, logistics, artificial intelligence, machine learning and cryptography. The race is on to build the world's first practical quantum computers, which requires scaling from arrays of a few dozen qubits, to thousands, to millions of qubits. To achieve this, we need to create integrated systems of qubit arrays and control electronics. In most implementations, the qubits require cryogenic cooling, typically to a fraction of a degree above absolute zero. Yet conventional CMOS electronics is designed to operate at room temperature, and if these chips are cooled to cryogenic temperatures, the operating characteristics of the transistors change markedly, and they no longer work as intended. This problem is well recognised in the industry. Major players such as Google, Microsoft and Intel have all invested in progressing towards building specialised "cryo-CMOS" control electronics that can operate in the very cold environment that the qubits require. Most quantum computing companies, however, don't have the resources to develop silicon CMOS processes for cryogenic temperatures. Instead, they rely on semiconductor fabrication via foundries (e.g., TSMC, Globalfoundries), looking to various silicon IP companies to provide technology to enable them to exploit the foundries' manufacturing capability. This model has worked well for development of chips for room temperature operation, however it requires significant updating to create new designs that can work at ultra-cold temperatures. This project brings together world-leading expertise in CMOS design and quantum computing. We will create updated process design kits (PDKs) for cryogenic temperatures and an ecosystem of silicon IP products to enable chip designers to exploit foundries using the established fabless model. Thus the project will enable quantum computing companies to scale their hardware systems to create a new generation of more powerful quantum computers.

Awaiting Public Project Summary

The crux of this application is to develop extremely low power, working samples of CMOS memory ‘chips’ suitable for customer evaluation on the latest 40nm Low Power process (40ULP) available from the leading global silicon foundry, TSMC. SureCore have already proven their power reducing concepts save up to 60% active power compared with 6 rival solutions in an independent test. The new 40ULP process released by TSMC has been specifically developed for portable, mobile, wearable, and energy scavenging products where battery life is key. The objective for SureCore is to become a leading vendor of Static Random Access Memory (SRAM) IP for integration into System on Chip (SoC) devices by semiconductor product suppliers. In order to achieve this, the power saving techniques must be proven on real silicon on the target process. This is the purpose of this application. SRAM memory is a key IP block essential to the development of SoC devices found in the majority of modern electronic products and will occupy up to 70% of SoC silicon area by 2017. This growth is driven by consumer demand for more features integrated into their mobile devices. However battery technology continues to lag consumer expectations; integrating more functionality means more memory which can consume up to 70% of battery power when active. The industry’s approach to date has been to reduce battery voltage but this approach has reached the end of the road; a rethink of the memory architecture is required. The secret of SureCore’s power saving technology is a re-design of the internal memory architecture without changing the external interfaces and with minimal change in performance. SureCore’s low power memory technology has attracted the attention of many global semiconductor companies who have expressed commercial interest if the benefits can be proven on the new 40ULP process. This project would achieve that, moving the company forward towards establishing commercial agreements.

This project aims to develop low power, working samples of CMOS memory ‘chips’ suitable for customer evaluation to prove the viability of SureCore’s novel architecture and circuit designs on a next generation, Fully Depleted Silicon-On-Insulator(FD-SOI) 28nm process technology. SureCore’s design will consume 40% less power than alternative solutions. Today’s smart phones, tablets and MP3 players are possible though System-on-Chip (SoC) devices which integrate much of their functionality. These devices rely on ‘Moore’s Law’ to cram more and more transistors onto a single silicon chip. Static Random Access Memory (SRAMs) can occupy over half the silicon area of a modern SoC and consume up to 70% of battery power. Quantum and atomistic effects are now influencing transistor characteristics reducing product yield and reliability; SRAM designs are particularly sensitive to these effects. Fundamental changes to the underlying transistor structures such as FD-SOI have been developed but cannot be easily adopted into existing design methodologies. SureCore recognise this challenge and through combining device physics knowledge with architecture and circuit design experience, they have developed a novel low power SRAM architecture. Simulation results indicate a power saving of 40%. This project will develop prototype silicon to prove the simulation results are accurate. SureCore can then sell these memory designs to the fabless semiconductor industry.