This project explores a new approach to memory architecture for energy-efficient Edge AI systems, focusing on early-stage feasibility assessment rather than physical chip development. As demand for AI capability moves rapidly from data centres into edge devices such as industrial systems, smart infrastructure, and embedded platforms, performance is increasingly constrained by memory access energy, latency, and predictability, rather than raw compute throughput. Memory has become a key bottleneck in delivering high performance per watt under tight power and cost constraints. Traditional approaches rely on fixed memory hierarchies and off-chip memory accesses, which can be inefficient and unpredictable for edge workloads. This project investigates whether alternative, memory-centric architectures - including those enabled by advanced 3D chiplet-based integration - can deliver better real-world performance and energy efficiency for Edge AI applications. The project will assess the technical and commercial feasibility of this approach through modelling, simulation, and architectural analysis, rather than hardware development. Key objectives include understanding performance-per-watt trade-offs, adaptability to evolving AI models, and the feasibility of chiplet-based memory architectures in edge systems, alongside practical integration considerations. Market engagement with potential customers will be used to validate use cases and adoption drivers. This is an evaluation and feasibility project, not a chip development programme. However, it lays the groundwork for a future commercial Edge AI accelerator by identifying whether memory-centric architectures can offer a compelling advantage over existing solutions. If successful, the work could support the development of new UK-designed technologies that improve the efficiency, flexibility, and deployability of AI at the edge, strengthening the UK’s position in energy-efficient computing and semiconductor innovation.